1. Field
Embodiments of the present invention pertain to the field of codeword decoding for data error correction, and more particularly to Bose-Chaudhuri-Hocquenghem (BCH) decoder architectures.
2. Description of Related Art
Data retrieved from memory devices, such as flash devices including NAND or NOR, DRAM memory devices, SRAM memory devices, magnetic medias, or data transferred over a communication channel may suffer errors for various reasons. Error correction schemes may be used to encode additional information for detection and/or correction of errors in the retrieved data.
Applications ranging from solid state drives to satellite communications are placing higher throughput demands on hardware responsible for the decoding of encoded data (i.e., codewords) received through a given channel. In the case of a storage controller, the decoding process can become a throughput limitation when hardware resources are limited (e.g., reduced controller chip area). In the case of a decoding engine for satellite communications, high bit error rates may again tax the decoding process to the point where the decoding hardware becomes a channel bottleneck.
BCH decoding is a popular technique employed for the correction of bit errors in a received codeword. Improved BCH decoder architectures which can increase the decoder throughput without incurring concomitant increases in gate count may achieve a given throughput with lower chip and overall system cost as well as reduced power consumption.